1. Field of the Invention
The present invention relates to the formation of high density integrated circuits and, more particularly, to the formation of high density dynamic random access memories.
2. Description of the Related Art
There is a continuing trend toward increasing the storage density of integrated circuit memories to provide increased levels of data storage on a single chip. Higher density memories provide storage that is generally more compact and is often cheaper on a per bit basis than an equivalent amount of storage provided on plural chips. It has generally been possible to provide these higher levels of storage at equivalent or improved levels of performance as compared to the earlier, less dense memory chips. Historically, the density of integrated circuit devices has been increased in part by decreasing the size of structures such as wiring lines and transistor gates as well as by decreasing the separation between the structures that make up the integrated circuit device. Reducing the size of circuit structures is generally referred to as decreasing the "design rules" used for the manufacture of the integrated circuit device.
In dynamic random access memories (DRAMs), information is typically stored by selectively charging or discharging each capacitor of an array of capacitors formed on the surface of a semiconductor substrate. Most often, a single bit of binary information is stored at each capacitor by associating a discharged capacitor state with a logical zero and a charged capacitor state with a logical one. The surface area of the electrodes of the memory capacitors determines the amount of charge that can be stored on each of the capacitors for a given operating voltage, for the electrode separation that can reliably be manufactured, and for the dielectric constant of the capacitor dielectric typically used between the electrodes of the charge storage capacitor. Read and write operations are performed in the memory by selectively coupling the charge storage capacitor to a bit line to either transfer charge to or from the charge storage capacitor. The selective coupling of the charge storage capacitor to the bit line is typically accomplished using a transfer field effect transistor (FET). The bit line contact is typically made to one of the source/drain electrodes of the transfer FET and the charge storage capacitor is typically formed in contact with the other of the source/drain electrodes of the transfer FET. Word line signals are supplied to the gate of the FET to connect one electrode of the charge storage capacitor through the transfer FET to the bit line contact facilitating the transfer of charge between the charge storage capacitor and the bit line.
FIG. 1 shows in schematic cross-section two memory cells of a DRAM at an intermediate stage of manufacture. The illustrated DRAM cells are formed on a P-type substrate 10 and include field oxide regions 12 to provide isolation from other, adjacent memory cells. A gate oxide layer 14 is formed by thermal oxidation on the active device region between the field oxidation regions and polysilicon gate electrodes 16 are formed on the gate oxide layer 14. The two gate electrodes 16 illustrated in FIG. 1 are incorporated into the two independent transfer FETs for the two illustrated memory cells. Polysilicon gate electrodes 16 are formed by depositing a layer of undoped polysilicon over the substrate, typically using low pressure chemical vapor deposition (LPCVD), and then implanting impurities into the polysilicon and activating the impurities to render the polysilicon layer conductive. The gate electrodes are then patterned using conventional photolithography techniques. A layer of silicon oxide 18 is provided over the polysilicon gate electrodes 16 to protect the gate electrodes in subsequent processing steps and, often, to serve as an etch stop for subsequent etching steps. Sidewall oxide spacer structures 20 are formed adjacent the gate electrodes when a two stage implantation process (discussed below) is used in the formation of the source/drain regions. At the same time that the gate electrodes 16 are formed, wiring lines 22 which connect different gate electrodes are formed on field oxide regions 12. Because the wiring lines are generally formed in the same process used to form the gate electrodes 16, the wiring lines have a structure similar to the gate electrodes. As illustrated, the wiring lines typically include polysilicon layers 22 covered by oxide layers 24 with sidewall oxide spacer structures 26 formed on either side of the polysilicon wiring lines 22.
Doped source/drain regions 28, 30 and 32 are formed on either side of the polysilicon gate electrodes 16 to define the channel regions of the transfer FETs. The source/drain region 30 that is common to the transfer FETs will serve as the bit line contact for the two illustrated transfer FETs. Lightly doped drain (LDD) structures are often used in small design rule memory transistors of the type that are primarily used in modem memory and logic devices. LDD source/drain regions 28, 30 and 32 are typically formed in a two step process, beginning with a relatively low level dopant implantation made self-aligned to the polysilicon gate electrodes 16. Spacer oxide regions 20 are then formed on either side of the gate electrodes 16 by first depositing by chemical vapor deposition (CVD) a layer of silicon oxide over the device and then anisotropically etching back the oxide layer to expose the substrate over the source/drain regions 28, 30 and 32. Etching back the CVD oxide layer produces the spacer oxide regions 20 on either side of the polysilicon gate electrodes 16 and on either side of the polysilicon wiring lines 22. After the spacer oxide regions 20 are provided on either side of the polysilicon gate electrodes 16, a second, heavier ion implantation is made into the source/drain regions 28, 30 and 32, self-aligned to the spacer oxide regions 20.
After the formation of the transfer FETs of the DRAM cells, conventional processing continues to form the charge storage capacitors by first depositing over the FIG. 1 structure a layer 34 of an insulating material such as CVD silicon oxide. The resulting structure is shown in FIG. 2. Openings 36 are then formed by conventional photolithography through the silicon oxide layer 34 to expose the source/drain regions 28, 32 of the substrate. Referring now to FIG. 3, a layer of undoped polysilicon 38 is next deposited by low pressure chemical vapor deposition (LPCVD) over the surface of the device and within the openings 36 in contact with source/drain regions 28, 32. Polysilicon layer 38 forms at least part of the lower electrode of the charge storage capacitor for the DRAM memory cells. The layer is doped, typically using N-type dopants, either in situ during deposition or by ion implantation and annealing and then the lower electrodes 38 are defined by photolithography. A capacitor dielectric layer, such as a two layer structure of silicon nitride and silicon oxide, is provided over the surfaces of the lower electrodes 38. Upper capacitor electrodes are then formed by depositing, doping and patterning a layer of polysilicon, as is well known.
Processing continues by blanket depositing a layer of interlayer dielectric material, such as a doped glass deposited by atmospheric pressure CVD from a TEOS source gas, over the DRAM structure. A bit line contact opening is formed through the dielectric layer by conventional photolithography to expose the common source/drain contact 30. A bit line contact is formed, typically consisting of one or more layers of metal deposited by sputtering or CVD over the device and in contact with common source/drain region 30 within the bit line contact opening. The bit line is then patterned and further processing is performed to complete the device.
Reducing the design rules used for forming the devices within a high density DRAM places heightened demands on many of the structures illustrated in FIGS. 1-3 and places heightened demands on the processing techniques used for forming the structures. Such demands on processing and the structures of the DRAM can reduce yields and increase the cost of the DRAM. It is therefore desirable to provide more manufacturable and more reliable methods of forming a DRAM.